Non-patent literature 1: “A 12.5 Gb/s SerDes in 65 nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery”, ISSCC Dig. Tech. Papers, pp. 436-591, FIG. 24.1.1, 2007.
Non-patent literature 1 discloses an example of a configuration in which an A/D converter performs an A/D conversion to a reception signal, and a waveform equalizer having a feed-forward equalizer (hereinafter, referred to as FFE) and a decision feedback equalizer (hereinafter, referred to as DFE) compensates an attenuation due to an inter symbol interference (hereinafter, referred to as ISI) in a transmission line.
When the waveform equalizer processes a reception data, the waveform equalizer operates so that tap coefficients of the FFE and the DFE are converged to an optimum value removing the ISI (also referred to as an adaptive equalization). However, when the waveform equalizer is used in a transmission line in which a reception signal is largely distorted due to the ISI, an influence of reflection, or the like, the tap coefficient may not be converged to the optimum value. This case may happen since an initial value of a tap coefficient is greatly different from an ideal value to which the tap coefficient should finally be converged and many errors may occur in a determination result of a detector (a slicer) disposed to an output stage.